Conventionally, a thin film transistor (hereinafter TFT) made of polycrystalline silicon has been in use as a switching element of a pixel part formed in an active matrix type liquid crystal panel. However, the TFT has a significant problem of having a large leak current when it is in an off state. If the leak current of the TFT is large, a signal voltage maintained in a pixel capacitance of each pixel part is reduced and the contrast of an image deteriorates. It is known that such a leak current becomes smaller, if an electric field concentration generated between a drain region and a channel region of the TFT is reduced. Also, there is a situation in which the breakdown voltage between the source region and the drain region needs to be improved. Accordingly, in order to reduce the electric field concentration between the drain region and the channel region and to improve the breakdown voltage between the source region and the drain region, the TFT provided with the LDD region is being produced.
FIGS. 15 to 19 are cross sectional views showing manufacturing steps of a conventional manufacture method of the TFT provided with the LDD region. Referring to FIGS. 15 to 19, the manufacture method of a bottom gate type TFT is described. As shown in FIG. 15, a gate electrode 123 made of a metal film is formed on a glass substrate 120. Next, as shown in FIG. 16, a gate insulating film 124 covering the glass substrate 120 including the gate electrode 123 is formed. Further, an amorphous silicon film is formed on the gate insulating film 124 and is laser annealed to form a polycrystalline silicon film 126. A photo resist is applied to the polycrystalline silicon film 126. By irradiating the photo resist with an exposure light from the back surface side of the glass substrate 20 (bottom side of FIG. 16), a resist pattern 129 is formed on the gate electrode 123 in a self-aligned manner. Next, phosphorus (P), which is an n type impurity, is ion-implanted to the polycrystalline silicon film 126 using the resist pattern 129 as a mask. As a result, a low concentration impurity region 128 with low concentration phosphorus doped and a channel region 127 without phosphorus implanted are formed in the polycrystalline silicon film 126.
As shown in FIG. 17, by further applying a photo resist on an upper surface of the polycrystalline silicon film 126 including the resist pattern 129 and exposing and developing the photo resist using a photo mask, a resist pattern 132 is formed. At this time, this resist pattern 132 is formed so as to cover the resist pattern 129 completely. Next, phosphorus is ion-implanted to the polycrystalline silicon film 126 using the resist pattern 132 as a mask. As a result, in the low concentration impurity region 128 of the polycrystalline silicon film 126, an LDD region 138 is formed adjacent to the channel region 127, and source/drain regions 139 with high concentration phosphorus doped therein is formed outside of the LDD region 138.
As shown in FIG. 18, an insulating film (not shown) is formed on the polycrystalline silicon film 126 and an etching stopper layer 135 is formed by etching the insulating film using the photolithographic method. Next, a metal film 136 is formed so as to cover the glass substrate 120 including the etching stopper layer 135. Further, a resist pattern 137 is formed on the metal film 136.
As shown in FIG. 19, a source electrode 143 and a drain electrode 144 are formed by etching the metal film 136 using the resist pattern 137 as a mask. The polycrystalline silicon film 126 is etched further using the resist pattern 137. As a result, the polycrystalline silicon film 126 is patterned in an island shape and becomes an active layer 141 of the TFT. This way, the TFT having the LDD region 138 is formed.
In Japanese Patent Application Laid-Open Publication No. 2000-228524, there is a description of forming a source region and a drain region of the bottom gate type TFT. These source and drain regions are formed by opening contact holes for connecting to a source electrode and a drain electrode outside of the polycrystalline silicon layer region that becomes an LDD region, and by ion-implantation high concentration phosphorus in these contact holes.